Merge pull request #22520 from hanliutong:hsv

Modify the SIMD loop in color_hsv.

* Modify the SIMD loops in color_hsv.

* Add FP supporting in bit logic.

* Add temporary compatibility code.

* Use max_nlanes instead of vlanes for array declaration.

* Use "CV_SIMD || CV_SIMD_SCALABLE".

* Revert the modify of the Universal Intrinsic API

* Fix warnings.

* Use v_select instead of bits manipulation.

modules/core/include/opencv2/core/hal/intrin.hpp

@@ -785,7 +785,6 @@ namespace CV__SIMD_NAMESPACE {
     OPENCV_HAL_WRAP_BIN_OP_LOGIC(v_int32)
     OPENCV_HAL_WRAP_BIN_OP_LOGIC(v_int64)
 
-
     #define OPENCV_HAL_WRAP_BIN_OP_MUL(_Tpvec) \
     inline _Tpvec v_mul(const _Tpvec& a, const _Tpvec& b) \
     { \

modules/core/include/opencv2/core/hal/intrin_rvv_scalable.hpp

@@ -639,6 +639,35 @@ OPENCV_HAL_IMPL_RVV_LOGIC_OP(v_int32, VTraits<v_int32>::vlanes())
 OPENCV_HAL_IMPL_RVV_LOGIC_OP(v_uint64, VTraits<v_uint64>::vlanes())
 OPENCV_HAL_IMPL_RVV_LOGIC_OP(v_int64, VTraits<v_int64>::vlanes())
 
+#define OPENCV_HAL_IMPL_RVV_FLT_BIT_OP(intrin) \
+inline v_float32 intrin (const v_float32& a, const v_float32& b) \
+{ \
+    return vreinterpret_f32m1(intrin(vreinterpret_i32m1(a), vreinterpret_i32m1(b))); \
+}
+OPENCV_HAL_IMPL_RVV_FLT_BIT_OP(v_and)
+OPENCV_HAL_IMPL_RVV_FLT_BIT_OP(v_or)
+OPENCV_HAL_IMPL_RVV_FLT_BIT_OP(v_xor)
+
+inline v_float32 v_not (const v_float32& a) \
+{ \
+    return vreinterpret_f32m1(v_not(vreinterpret_i32m1(a))); \
+}
+
+#if CV_SIMD_SCALABLE_64F
+#define OPENCV_HAL_IMPL_RVV_FLT64_BIT_OP(intrin) \
+inline v_float64 intrin (const v_float64& a, const v_float64& b) \
+{ \
+    return vreinterpret_f64m1(intrin(vreinterpret_i64m1(a), vreinterpret_i64m1(b))); \
+}
+OPENCV_HAL_IMPL_RVV_FLT64_BIT_OP(v_and)
+OPENCV_HAL_IMPL_RVV_FLT64_BIT_OP(v_or)
+OPENCV_HAL_IMPL_RVV_FLT64_BIT_OP(v_xor)
+
+inline v_float64 v_not (const v_float64& a) \
+{ \
+    return vreinterpret_f64m1(v_not(vreinterpret_i64m1(a))); \
+}
+#endif
 
 
 ////////////// Bitwise shifts //////////////