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Merge pull request #15061 from AsyaPronina:dev/fix_merge_issue

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Alexander Alekhin 2019-07-16 21:00:50 +03:00 committed by GitHub
commit f6ec0cd827
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3 changed files with 0 additions and 6 deletions
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2
modules/gapi/test/cpu/gapi_core_tests_cpu.cpp
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@ -440,7 +440,6 @@ INSTANTIATE_TEST_CASE_P(BackendOutputAllocationTestCPU, BackendOutputAllocationT
Combine(Values(CV_8UC3, CV_16SC2, CV_32FC1),
Values(cv::Size(50, 50)),
Values(-1),
Values(false),
Values(CORE_CPU)));
INSTANTIATE_TEST_CASE_P(BackendOutputAllocationLargeSizeWithCorrectSubmatrixTestCPU,
@ -448,6 +447,5 @@ INSTANTIATE_TEST_CASE_P(BackendOutputAllocationLargeSizeWithCorrectSubmatrixTest
Combine(Values(CV_8UC3, CV_16SC2, CV_32FC1),
Values(cv::Size(50, 50)),
Values(-1),
Values(false),
Values(CORE_CPU)));
}

2
modules/gapi/test/cpu/gapi_core_tests_fluid.cpp
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@ -258,7 +258,6 @@ INSTANTIATE_TEST_CASE_P(BackendOutputAllocationTestFluid, BackendOutputAllocatio
Combine(Values(CV_8UC3, CV_16SC2, CV_32FC1),
Values(cv::Size(50, 50)),
Values(-1),
Values(false),
Values(CORE_FLUID)));
INSTANTIATE_TEST_CASE_P(BackendOutputAllocationLargeSizeWithCorrectSubmatrixTestFluid,
@ -266,7 +265,6 @@ INSTANTIATE_TEST_CASE_P(BackendOutputAllocationLargeSizeWithCorrectSubmatrixTest
Combine(Values(CV_8UC3, CV_16SC2, CV_32FC1),
Values(cv::Size(50, 50)),
Values(-1),
Values(false),
Values(CORE_FLUID)));
//----------------------------------------------------------------------

2
modules/gapi/test/gpu/gapi_core_tests_gpu.cpp
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@ -383,7 +383,6 @@ INSTANTIATE_TEST_CASE_P(BackendOutputAllocationTestGPU, BackendOutputAllocationT
Combine(Values(CV_8UC3, CV_16SC2, CV_32FC1),
Values(cv::Size(50, 50)),
Values(-1),
Values(false),
Values(CORE_GPU)));
// FIXME: there's an issue in OCL backend with matrix reallocation that shouldn't happen
@ -392,7 +391,6 @@ INSTANTIATE_TEST_CASE_P(DISABLED_BackendOutputAllocationLargeSizeWithCorrectSubm
Combine(Values(CV_8UC3, CV_16SC2, CV_32FC1),
Values(cv::Size(50, 50)),
Values(-1),
Values(false),
Values(CORE_GPU)));
//TODO: fix this backend to allow ConcatVertVec ConcatHorVec