Maksim Shabunin 9efaa3cce7 RISC-V/RVV 0.7: v_add/v_sub saturation and avoiding 64-bit register in v_check_

2023-01-30 23:25:53 +03:00

..

core

RISC-V/RVV 0.7: v_add/v_sub saturation and avoiding 64-bit register in v_check_

2023-01-30 23:25:53 +03:00

core.hpp

add cv::flipND; support onnx slice with negative steps via cv::flipND

2022-12-23 16:39:53 +08:00